FIFO IC Distributor

FIFO IC Distributor in China

  • High speed, low power bidirectional clocked memory.
  • Provide a rapid and simple link to other structures.
  • High-performance application, such as networking, wireless base stations,etc.
  • Used in communications and networking, bridges, routers and many other applications
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Reliable FIFO IC Supplier - Rantle East Electronic

RANTLE provides FIFO IC that is high speed, low power bidirectional clocked memory. It has two independent 512 ×18 dual-port SRAM FIFOs on the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions, a half-full flag, and a programable almost-full/almost-empty flag.

RANTLE is distributor of FIFO IC with synchronous FIFO, asynchronous FIFO, queuing FIFO and bi-directional FIFO products to help designers solve inter chip communications protocol problems, such as rate matching, buffering and bus matching. The parallel FIFO structures allow formulation of any word size while serial FIFO communications provide a rapid and simple link to other structures.

FIFO IC Supplier

RANTLE FIFO IC has parallel FIFO solutions for high-performance application, such as networking, wireless base stations, graphics, medical imaging, data acquisition and industrial automation.

Cost-effective parallel FIFO solutions for multimedia products for graphics, MP3 and other consumer applications.

FIFO IC Wholesaler

Furthermore, RANTLE FIFO IC are widely used in communications and networking, bridges, routers and many other applications that requires sequential data processing. Also, FIFO IC provides completely independent 8bit input and output ports that can operate at a maximum speed of 80MHz. it provides a straightforward bus interface to serially read/write memory that can reduce inter-chip design efforts.

FIFO IC Disributor

RANTLE has a wide and unobstructed channel for supply source and reserves a large number of electronic components. We have gradually established an excellent reputation and credibility in our international business for almost 16 years.

RANTLE offers accurate quotations, excellent credit, reasonable price, reliable quality, fast delivery, and authentic service.


Now we have got an excellent international commercial reputation and public praise among the customers. We have founded a long-term business relationship with more than one hundred global famous electronic companies.

RANTLE is the best supplier of FIFO IC and other electronic components. For inquiries just contact our hardworking sales team now.

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Related Electronic Components: N25Q128A13ESF40F , MCP23017-E/SP , DS1216C , AD9833BRMZ

FIFO IC: The Ultimate FAQ Guide

If you have been wondering what FIFO IC is, its features, specification, use, packaging, reading and erasing techniques, you are in the right place.

Today’s guide will answer all your questions about the FIFO integrated circuit.

The best part – by the end of this guide, you will have a comprehensive knowledge of this memory IC.

Let’s have a look:

What is FIFO IC?

FIFO is an acronym for First In, First Out.

A FIFO IC provides temporal storage of data in a computerized system. Data stored is typically in transit from one process to another.

Data from a FIFO IC chip is supplied in line with the FIFO logic of releasing the oldest data first.

FIFO ICs buffer applications between devices running at different speeds of operation. They also provide temporal storage for data waiting for enhanced processing.

FIFO ICs are additionally useful in connecting digital devices with differing rates of data production and consumption.

FIFO IC illustration

FIFO IC illustration

Why do we need Asynchronous FIFO ICs?

Asynchronous FIFO ICs are useful in that they safely transfer data between two different clock domains.

Here, data words are written in one clock domain to a FIFO buffer and then read from the other domain.

Where are FIFO ICs used?

You will find FIFO ICs in communications and networking applications.

Computer networks employ FIFO ICs in network bridges and routers to hold packets of data transiting to other points of application.

What are the Types of FIFO ICs?

You find two types of FIFO ICs: Exclusive Read/Write FIFO IC and Concurrent Read/Write FIFO IC.

1. Exclusive Read/Write FIFO IC

In this FIFO IC type, how the data is read defines how the data is written. The write clock has a timing relationship with the read clock.

As such, there cannot be an overlap of the two clocks.

Exclusive Read/Write FIFO ICs can be used for two different systems working independently of each other.

This is by employing an external circuit to synchronize the two systems. However, synchronizing reduces the rate of data transfer significantly.

2. Concurrent Read/Write FIFO

How you read data in a concurrent FIFO IC is not defined by how you write the same data.

As the name suggests, data can be written and read concurrently, that is, at the same time. Nonetheless, you can also complete a write process first before commencing a read.

A Concurrent Read/ Write FIFO IC can be used to connect two different systems with differing frequencies.

You do not need to use an external circuit to synchronize the two systems.

The Concurrent Read/Write FIFO IC can be categorized into two depending on the control signals used for read or write process.

These are; the synchronous FIFO IC and the asynchronous FIFO IC.

What are the Advantages of FIFO ICs?



You find FIFO ICs useful in the following ways:

  • FIFO ICs prevent loss of data in high-speed communication systems.
  • There is an increased bandwidth when utilizing FIFO ICs in network connections.
  • FIFO ICs allow digital circuits that operate at dissimilar rates to be interconnected.
  • In data streams, FIFO ICs make it possible to carry out timing corrections.

Are there Limitations of FIFO ICs?

When using FIFO ICs, you realize that they are unable to distinguish packets of data based on their service class.

As such, data transmitting in short bursts will be given priority over other data flows.

What are the Components of a FIFO IC?

FIFO IC Schematic

FIFO IC Schematic

A FIFO IC generally comprises circuitry for storage and two pointers to execute read and write operations.

How does an Exclusive Read/Write FIFO Operate Asynchronously?

For an Exclusive Read/Write FIFO IC to operate asynchronously, the timing conditions of the read and write inputs are important.

The timing conditions have to be maintained to guarantee proper device functionality.

The pulse widths of the Write Clock and Read Clock signals should be kept at minimum levels. A value of 60 and 30 nanoseconds respectively will suffice.

Also, note that a read operation should be delayed by one-twentieth of a microsecond after a write process.

With the read and write signals originating from systems working independently of each other, use a circuit allowing for synchronization.

This will guarantee proper functioning even in the case of the simultaneous appearance of the two signals.

In the event of concurrent arrival of both the Write and Read signals, the read operation is given priority.

You need to determine also the highest frequency possible for the Clock Signal. The minimum length of the Write Signal is provided for as 60 ns.

Besides, you need to define the minimum time during which the clock signal is low.

The time delay between the write and read affairs equals the least possible instance for a high clock signal.

In what Architectures can FIFO IC be implemented?

You can find FIFO Integrated Circuits in two architectures:

· Fall through FIFO IC

The first generation of FIFO ICs constituted fall through FIFO ICs. The fall through FIFO IC follows the queuing theory in its operation.

In a queue, the individual at the head of the queue is first served. Once done, every member in the queue moves forward one step and the next individual atop the queue is served.

This goes o until the last individual in the queue is served.

A fall through FIFO IC stores data in a latch cascade with a clock generator for data control. Fresh data slips through the entire cascade before settling at the furthest storage location.

The endured data word is picked first for a read before the other data values move along in the queue.

These clock pulses move the data word to the last free latch. The clock generator indicates the state of a latch whether it is empty or contains a data word.

How long a data word takes to be red form the time it was written is called the fall-through time.

One disadvantage with the fall though is that it requires for every data word a status flip-flop. This is only effective with short FIFOs.

With long FIFOs, it contributes to the long fall through time.

This architecture is presently outdated.

· FIFO IC with Static Memory

This architecture was developed to remedy the extended fall through time in long FIFO ICs. It eliminated the need to move data words through every memory location.

This is through the provision of a memory with a circular structure and a pair of pointers.

Here, the write pointer contains the incoming data’s memory address.

The write pointer, on completion of a write operation, is fixed to the succeeding memory location.

Similarly, completion of the reading process results in the fixation of the read punter to the following data word.

You will find the read pointer persistently trails the write pointer. When it finally twins the write pointer the FIFO IC is considered “empty”.

The reverse where the write pointer mates the read pointer is regarded as a “full’ FIFO IC.

A FIFO IC with Static Memory utilizes for storage, a two-port static RAM.

The pointers assume the role of binary counters producing the static Ram’s memory addresses.

The read and write pointers identify the location of data for the read or write process respectively.

Control blocks direct the input and output of data with truth bits providing “full” or “empty” signals.

You will also find FIFO ICs generating signals such as Almost Empty, Almost Full and Half Full. You also need to reset a FIFO IC with static memory.

This helps to return the pointers and logic status to their prescribed default states.

An advantage of the FIFO IC with static memory is that its fall-through time is not dependent on its length.

This makes the creation of swift FIFO ICs with thousands of words in length conceivable.

Working out the circuit of the control logic is not noticeably affected by the length of the FIFO IC.

This is because the only features needing expansion are flag logic parts and the pointers.

This type of architecture is to be found in today’s FIFO ICs.

How do Synchronous and Asynchronous FIFO ICs compare?

FIFO Full and empty memory illustrations

FIFO Full and empty memory illustrations

The asynchronous and synchronous FIFO ICs are the two types of Concurrent read/write FIFO ICs.

The classification into synchronous or asynchronous is determined by the control signals used for writing and reading.

The synchronous FIFO IC encompasses a design where the reading and writing of the FIFO buffer are carried out in the same domain.

It constitutes a control logic that controls the read and writes pointers in addition to generating status flags.

It can also provide handshake signals that could be interfaced with user logic.

The asynchronous FIFO IC constitutes a design with two clock domains that are asynchronous to each other.

Here, one clock domain writes the data values to the FIFO buffer and the other clock domain reads from it.

As such, asynchronous FIFO ICs transfer data from one clock domain to another.

· Asynchronous FIFO IC

An asynchronous FIFO has two control lines used in writing data: the Write Clock and Full. Before writing a value of data into an asynchronous FIFO, the availability of space is checked. This is enabled through checking the status line for Full signal.

Data can only be written into a FIFIO IC if there is available accommodation for it.

The procedure is undertaken by a Write Clock whereas to output a data value requires a Read Clock.

Data can only be read out if it is presently located in the FIFO IC and is atop the hierarchy.

The asynchronous FIFO has the drawback of not fully synchronizing the read and write clock with the status signals.

· Synchronous FIFO ICs

Asynchronous FIFO IC entails control in the manner of those in processor systems.

Such a system works in sync with a clock signal for the whole system.

The timing of the system is bound to proceed even in the absence of executable actions.

The write and read process of asynchronous FIFO IC is initiated by Chip-select signals.

Asynchronous FIFO IC needs two free-running clocks, each from the writing and reading system.

To enable the writing process, the Write Enable input and the Write Clock should be synchronous.

The free-running clock can wholly synchronize the Full status line with the Write Clock.

Similarly, with the Read Enable synchronous with the Read Clock, data values can be read out by a low level.

The free-running clock in this case too allows total synchronization of the Read Clock with the Empty Signal.

This way, synchronous FIFO ICs can be amalgamated into common processor designs. This is because they provide total synchronization of the specific free-running clock with the Full and Empty status signals.

The status lines are orchestrated with the clock signals just as the “full” line is with the write prompt. The Read Clock coordinates with the cue for “empty”.

What are the Quality Standards for FIFO IC?



You will find several standards for the FIFO IC depending on the application. Some standards include:

  • DESC-DWG-5962-94707: For a 2K x 9 Parallel-Synchronous FIFO IC
  • DESC-DWG-5962-99615: For a 64K x 9 Asynchronous FIFO IC
  • SMD 5962-08208: For a 1K X 36 Clocked FIFO IC
  • MIL-M-38510/250: For a 512 X 9 Dual Port Memory FIFO IC

How does FIFO IC Work?

A FIFO ICs working is executed as a circular queue with two pointers: the read pointer and the write pointer.

The pointers are also referred to as address registers.

Both pointers are usually at the initial location of memory and the queue for FIFO identification, empty.

When the read pointer mates with that of the write, it motions an “empty” response on the IC. Otherwise, when the write pointer couples the read pointer, a “full” siren is provided.

How do you Test the FIFO IC?

You can use a Hardware Verification Language such as SystemVerilog. Here, you can create a highly effective test for a design under test with SystemVerilog.

Also, you can create a verification environment that could be used repeatedly on other design projects.

Other approaches in testing a FIFO include.

· Coverage Driven Verification (CDV)

This verification method provides an efficient test bench environment that queries all the features in a FIFO IC design.

It also greatly reduces the time taken to carry out a verification procedure for the whole design.

A CDV’s test bench components are reusable and scalable allowing for the verification of sophisticated designs.

This is in addition to features that allow the prompt realization of the test goals.

A CDV can utilize the constructs of SystemVerilog to stir the stimulus generator into producing verification stimuli for all design features.

Therefore, the environment of a CDV test bench can support directed testing of the FIFO IC and also constrained-random testing.

It is noteworthy that the constrained-random testing minimizes the difficulties of manual test writing.

Writing test cases manually consumes plenty of time and is impossibly challenging to achieve in case of intricate designs.

· Assertion-Based Verification (ABV)

This method entails the use of assertions in the test bench to check the functionality of a FIFO design under test. Assertions are statements of conditions that are examined for either their truthfulness or falseness by a method particular to a designer.

The statements of conditions aid in determining the conduct of a FIFO design under test. It can also be rigged to produce an alarm for a design’s inconsistent functioning.

It has been established that using ABV greatly reduces the verification period and therefore the efficiency of verification.

The assertion is of two kinds: Immediate and concurrent assertion.

The immediate assertion is applied where the instantaneous response of a FIFO design is paramount on the application of a condition.

The concurrent assertion is applied where response by the design is observed after a few cycles on setting the condition.

Assertions are prone to mistakes in sophisticated designs. You can debug the assertions by using a model that executes the pattern matching.

Such a method includes three-state visualization and model.

What is Gray Code Pointers for in FIFO ICs?

Grey code FIFO pointer

Grey code FIFO pointer

Gray code pointers are a feature of asynchronous FIFO ICs.

With gray code pointers, only one bit changes when shifting from one value to another.

This is unlike a binary counter where an increment results in the changing of several bits.

With an asynchronous system having two domains, the gray code pointer cannot be inconsistently sampled in the other domain.

What is a First-Word Fall-Through FIFO IC?

A First-Word Fall-Through is a FIFO IC type where the first word written into the FIFO appears on the output immediately.

This way, the first word is read on the subsequent clock cycle without sending a signal to the Read Enable.

In addition to reading the word, you can simultaneously signal the Write Enable high.

This provides the availability of the next data word on the output on the following clock cycle.

What are some of the Features of FIFO ICs?

You find the following features of FIFO ICs imperative.

  • The FIFO IC’s memory density is provided in bits.
  • The number of words a chip can store.
  • The bits required for every word.
  • The range of temperature at which a FIFO IC can work.
  • A FIFO IC chip’s voltage requirement.

Can you extend the Word Width of a FIFO IC?

Yes, you can.

The word width of FIFO ICs is easily expanded since all FIFO ICs’ control inputs have parallel connectivity.

Can you enhance a FIFO IC’s Memory Depth?

Yes, you can.

Asynchronous FIFO IC’s memory depth is effortlessly expanded by configuring individual FIFO ICs using the fall-through principle.

For the transfer of data between the FIFO ICs, an extra clock signal is used.

A clock pointer’s number of complete cycles in a second will determine the FIFO IC’s fall-through time and speed.

These parameters do not however influence the amount of data exchanged during the read or write process.

How are FIFO ICs used to connect Peripherals to Processors?

FIFO ICs are used to connect peripherals to processors due to the improved speeds of modern processors over peripherals.

FIFO ICs are used to allow processors to maintain their speed while exchanging data with a peripheral.

The same applies to cases where peripherals are faster than processors only employing different circuit elements.

Where a processor has to read data from a unidirectional peripheral, a FIFO IC buffers some of the input data.

It then employs an interrupt, triggered by a Full, Half Full or Almost Full flag. This interrupt allows the processor to read the data.

In the event the peripherals connected are bidirectional such as a serial port, a bidirectional FIFO IC is used.

Such a FIFO IC constitutes two stand-alone FIFO ICs.  Each FIFO IC has a width and depth of 9 bits and 1024 words respectively.

FIFO Schematics

FIFO Schematics

How do FIFO ICs carry out block data transfer?

In block data transfer, data is split into blocks and transferred via data lines.

A FIFO IC with a Half Flag is used to enable high-speed conversion of data into blocks. In addition, its depth should be equivalent to two times the block size.

At a Half Full flag, the controller responsible for sending the data block begins the transfer process.

The controller typically entails a counter and a couple of gates. Data can be written into the FIFO IC while the transfer is carried out.

How do you carry out Programmable Delay with FIFO ICs?

You can implement a programmable delay by applying an Almost Full/Almost Empty flag and an inverter to the FIFO IC.

For a delay of n clock cycles, you program the AF/AE flag to the value n-2.

A FIFO IC continuously fills when data is written into it until the stored data words correspond to the programmed value.

After two clock cycles then, the AF/AE flag changes to a low level.

The double delay of the clock cycles arises from the coordinated consolidation of numerous almost full and empty flags.

With inverter actualization, the flag starts reading the data words in the FIFO IC output.

This causes the FIFO IC to function as a fixed-length shift register.

How can FIFO ICs be used to Collect Data before an event?

To collect data before an event, you use a circular memory that is impeded from taking in data by the event.

A FIFO IC fits the profile.

On resetting the FIFO IC, the delayed AF input signal is used to program the AF/AE flag.

The sum of values to be immured prior to the event is permutated as a discrete value.

Thereafter, the input sigil is altered to “high” allowing the commencement of the loading drill.

Integrated multilevel synchronization causes the AF/AE flag to commence two clock cycles after the programmed value.

Hereafter, the excess words are read out by the FIFO IC.

After the occurrence of the event, the input signal of the Trigger Window changes to a low level.

This is followed by the reading of another data word and eventually the reset of the AF/AE signal. This stops the output of data.

How are FIFO ICs used to Collect Data before and after an Event?

Like in collecting data before an event, the AF/AE flag is used to collect data before and after.

A flip-flop, set and permitted to capture data by the Trigger Window, is used to move the written input.

The input sigil is administered “low” in the wake of an event.

In the wake of an event, data is consumed into the FIFO IC up until a point where the input cue degenerates to a “low” level.

The flip flop is then returned to a zero state.

A logic gate able to output only one value is distanced on a path from the almost full or empty truth-bit.

This gate is responsible for the constriction of data reading post eventum.

What Packaging is used for FIFO ICs?

You will find the following packages typical for FIFO ICs depending on their application.

  • Ball Grid Array (BGA)
  • Single In-line Package (SIP)
  • Dual In-line Package (DIP)
  • Quad Flat Package (QFP)

 What do you Consider when Selecting a FIFO IC?

When selecting a FIFO IC, you need to consider the following aspects principally associated with its performance.

  • The FIFO IC’s access time given in nanoseconds.
  • The data rate of the FIFO memory chip provided in hertz (Hz).
  • The data setup and hold time.
  • The FIFO IC’s fall-through time.

With the information in this guide, you should be able to choose a suitable FIFO IC.

However, if you have questions, or looking for high-performance FIFO IC; Rantle team can help.

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